Conventional non-volatile semiconductor devices include various types of flash memory devices, electrically programmable read only memory (EPROM) devices and electrically erasable programmable read only memory (EEPROM) devices. Such conventional types of memory devices are generally characterized by a floating gate and an electrical connection called a control gate, typically fabricated from polycrystalline silicon doped with an appropriate doping material to render the polycrystalline conductive, e.g., phosphorous. The floating gate is separated from a substrate region by a gate dielectric or tunnel dielectric layer of insulating material while the substrate region includes symmetrical or asymmetrical source/drain regions defining a channel region therebetween. The floating gate and control gate are typically separated by a layer of insulating material characterized as an interpoly dielectric layer.
EEPROMs are typically programmed by applying a voltage to the control gate so that electrons or a charge tunnel through the tunnel oxide layer and is stored on the floating gate in a capacitive manner. Erasing is implemented by grounding the control gate and causing electrons or charge to tunnel through the tunnel dielectric layer to the substrate. Typically, electrons tunnel through the tunnel dielectric layer by a phenomenon called "Fowler-Nordheim" tunneling. A conventional EEPROM is disclosed by Mukherjee et al., U.S. Pat. No. 4,868,619 and comprises an asymmetrical drain-source junction.
The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices requires design rules of 0.18 microns and under, increased transistor and circuit speeds, sharp junctions, high reliability and increased manufacturing throughput for competitiveness. The reduction of design rules to 0.18 microns and under generates numerous problems challenging the limitations of conventional semiconductor technology.
Non-volatile memory cells occupy a significant amount of precious real estate on a semiconductor substrate and, hence, pose a serious impediment to miniaturization. Moreover, the protrusion of the gate electrodes above the main surface of a substrate results in the formation of a significant step portion which is difficult to planarize, thereby challenging the depth of focus limitations of conventional photolithographic techniques.
In copending U.S. patent application Ser. No. 08/882,961 filed on Dec. 18, 1997 and in copending application Ser. No. 08/993,890 filed on Dec. 18, 1997, semiconductor devices are disclosed comprising dual non-volatile memory cells, each comprising a substantially U-shaped floating gate electrode in a trench formed in the semiconductor substrate and a substantially T-shaped control gate electrode filling the trench and extending on the substrate.
In copending U.S. patent application Ser. No. 09/026,358 filed on Feb. 19, 1998, a semiconductor device containing double density non-volatile memory cells is disclosed, wherein each double density non-volatile memory cell contains a floating gate within a trench formed in a substrate and a control gate formed thereon.
There exists a continuing need for semiconductor devices with increased density and highly reliable deep sub-micron features. There exists a particularly need for reliable semiconductor devices containing dense non-volatile memory cells with increased channel lengths.